GXSC ADC Replaces AD9689 in Software-Defined Radio Systems

Software-Defined Radio (SDR), with its core advantages of hardware-software decoupling, flexible and adjustable frequency bands, and software-reconfigurable functionality, has become a core technology in the fields of modern wireless communications, radar detection, and satellite communications. The performance of software-defined radio systems primarily hinges on the digitization of RF signals. Conventional low- to medium-speed, narrowband ADCs rely on multi-stage mixing and downconversion analog circuits to expand the receive bandwidth.

By employing a high-speed RF direct-sampling ADC, this system can directly digitize high-frequency RF signals, eliminating the need for multi-stage analog downconversion chains, thereby simplifying the system architecture and enhancing signal integrity. This system recommends the use of the GXSC high-performance dual-channel 14-bit 2.6 GSPS high-speed analog-to-digital converter, which effectively addresses the issues of insufficient bandwidth, limited accuracy, and complex signal paths found in traditional SDR devices.

The GXSC ADC integrates two independent high-performance ADC cores and features an on-chip buffer, designed to support communication applications that require direct sampling of wideband analog signals up to 5 GHz. This ultra-high sampling rate allows it to easily cover signals across multiple frequency bands, including RF and IF, meeting the compatibility requirements of multimode digital receivers for different communication standards. The device offers advantages such as wide input bandwidth, high sampling rate, excellent linearity, a small package, and low power consumption.

GXSC ADC Product Advantages:

Package size is compatible with the reference model, supporting functional replacement of the AD9689

Power consumption is approximately 60% of the reference chip, effectively reducing the overall power consumption of the system solution

Wide operating temperature range of -55°C to +105°C, with robust performance across the entire range

Compact FCBGA196 plastic-encapsulated package, effectively reducing system size

High integration, incorporating digital downconversion and a filter, which helps reduce system costs

204B high-speed interface, facilitating user layout and routing

Full-power bandwidth: 6.0 GHz

Full-power bandwidth: 6 GHz (-3 dB)

Dynamic performance (fs = 2.4 GSPS, input signal power -2 dBFS)

-fin = 155 MHz; ENOB = 9.42 bits, SFDR = 72.94 dBFS, SNR = 59 dBFS

-fin = 750 MHz; ENOB = 9.23 bits, SFDR = 68.42 dBFS, SNR = 57.9 dBFS

-fin = 900 MHz; ENOB = 9.17 bits, SFDR = 69.34 dBFS, SNR = 57.3 dBFS

-fin=1800 MHz; ENOB=8.96 bits, SFDR=66.68 dBFS, SNR=56.3 dBFS

-fin=2100 MHz; ENOB=8.74 bits, SFDR=65 dBFS, SNR=55 dBFS

-fin=3300 MHz; ENOB=8.3 bits, SFDR=60.2 dBFS, SNR=52.5 dBF

This domestically produced analog-to-digital converter also features several functions that simplify automatic gain control (AGC) in communication receivers; the programmable threshold detector allows the use of the fast detection control bit in the ADC registers to monitor the power of the incoming signal. In addition to the fast detection output, the device provides signal monitoring capabilities. The signal monitoring module offers additional information about the signal being digitized by the ADC. Users can configure the acceptable channel data rate based on the data and the receiving logic device, and configure the FJESD204B-based Subclass 1 high-speed serial output for various channel modes, including single-channel, dual-channel, quad-channel, and octal-channel modes. The ADC supports multi-device synchronization via the SYSREF+ and SYNCINB± input pins.